Electronic devices for data processing and data communication are generally designed to permit fast data transmission between semiconductor circuits. For example, in those portions where especially fast operations are needed, bipolar semiconductor circuits including emitter coupled logics (ECL) are used, while in other portions CMOS semiconductor circuits are used.
In cases when coexisting semiconductor circuits have different characteristics as mentioned above, the operating levels of the semiconductor circuits may be different. Accordingly, an output of a semiconductor circuit may not be directly coupled to other semiconductor circuits.
Conventionally, when the output level of a first semiconductor circuit is different from the input level of a second semiconductor circuit to be connected with the first circuit, a level converter is provided between the two so that the output level of the first circuit is adjusted or matched to that of the second circuit.
A typical converter 5 shown in FIG. 1 is installed between an output buffer 2 for a CMOS circuit 1 consisting of CMOS semiconductors and an input buffer 4 for a bipolar circuit Such inverter is designed to convert the level of the logic signal SO of the CMOS circuit 1 to the level of the input SI of the bipolar circuit 3.
The level converter 5 interfaces a CMOS circuit coupled with a bipolar circuit, and may convert the logic level of the CMOS circuit in the range of 0-5 volts to the logic level of the ECL (bipolar logic) in the range of -0.8.about.-1.7 volts.
However, such prior art devices have the following disadvantages.
Firstly, it requires an independent converter 5, which implies that additional components are required in manufacturing an electronic device, thereby not only adversely affecting the cost efficiency of the device but also requiring extra space within the substrate. Furthermore, the converter requires extra electric power.
Another serious problem pertinent to such devices is that when the distance between the CMOS circuit 1 and the converter 5 is long, floating capacity formed in the circuit board bearing them becomes so great that the operational speed of the CMOS circuit 1 will be lowered for a large output load. This impedes fast signal transfer between the circuits.